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## Uses of Interface
rdlc.hw.Link

Packages that use Link
rdlc.hw | This package contains all the classes to transform an RDL design into a hardware design.
rdlc.hw.verilog | Classes for turning an abstract hardware design into Verilog.

Uses of Link in rdlc.hw

Subinterfaces of Link in rdlc.hw
`interface` | `ExternalLink` Abstract representation of a link which can transport messages off this platform (FPGA).

Classes in rdlc.hw that implement Link
`class` | `Link_Standard` Standard link generator class from which most links can inherit.

Methods in rdlc.hw that return Link
`Link` | `Library.createLink(java.lang.String linkName, boolean accurateSim, Log errorLog)` Create a link of the given type.

Uses of Link in rdlc.hw.verilog

Classes in rdlc.hw.verilog that implement Link
`class` | `RegisterLink` A simple register link generator class.
`class` | `SerialLink` A simple synchronous bit serial link generator class.

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