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## Uses of Class
rdlc.hw.ModuleWireGroup

Packages that use ModuleWireGroup
rdlc.hw | This package contains all the classes to transform an RDL design into a hardware design.
rdlc.hw.verilog | Classes for turning an abstract hardware design into Verilog.

Uses of ModuleWireGroup in rdlc.hw

Fields in rdlc.hw declared as ModuleWireGroup
`protected static ModuleWireGroup` | `ModuleWireGroup.RAMPHostControls` The standard RAMP host controls port group.
`protected static ModuleWireGroup` | `ModuleWireGroup.RAMPLinkControls` The standard RAMP link controls port group.
`protected static ModuleWireGroup` | `ModuleWireGroup.RAMPStartDone` The standard start and done port group.
`protected static ModuleWireGroup` | `ModuleWireGroup.RAMPSystemInputs` The standard system inputs port group.

Methods in rdlc.hw that return ModuleWireGroup
`ModuleWireGroup` | `AggLink.getAggregateWires()` Simple accessor.
`ModuleWireGroup` | `ExternalLink.getExternalWires()` Simple accessor.
`ModuleWireGroup` | `Engine.getExternalWires()` Simple accessor.
`ModuleWireGroup` | `AggLink.getInternalWires(java.lang.String branch)` Simple accessor.
`ModuleWireGroup` | `Link.getWires(boolean input)` Simple accessor.
`static ModuleWireGroup` | `ModuleWireGroup.RAMPHostControls()` Create the standard RAMP host controls port group.
`static ModuleWireGroup` | `ModuleWireGroup.RAMPLinkControls()` Create the standard RAMP link controls port group.
`static ModuleWireGroup` | `ModuleWireGroup.RAMPStartDone()` Create the standard start and done port group.
`static ModuleWireGroup` | `ModuleWireGroup.RAMPSystemInputs()` Create the standard system inputs port group.

Methods in rdlc.hw with parameters of type ModuleWireGroup
`boolean` | `ModuleInstance_Indirect.connect(ModuleWireGroup connection, boolean useAttributes)` Connect the wire group in the instantiated module to the same wire group in the module in which this instantiation exists.
`boolean` | `Module.connect(ModuleWireGroup target, ModuleWireGroup source)` Connect two wire groups within this module.
`boolean` | `ModuleInstance_Indirect.connect(java.lang.String wireGroupName, ModuleWireGroup connection)` Connect the wire group in the instantiated module to the wire group given.
`abstract void` | `ModuleInstance_Standard.Message_Fixed.generatePack(ModuleParameterGroup portParamGroup, ModuleWireGroup packWireGroup, int widthBits, int extraWidth)` Generate the packing logic for this message object.
`void` | `ModuleInstance_Standard.MessageSimple.generatePack(ModuleParameterGroup portParamGroup, ModuleWireGroup packWireGroup, int widthBits, int extraWidth)`
`void` | `ModuleInstance_Standard.MessageStruct_Fixed.generatePack(ModuleParameterGroup portParamGroup, ModuleWireGroup packWireGroup, int widthBits, int extraWidth)`
`void` | `ModuleInstance_Standard.MessageUnion_Fixed.generatePack(ModuleParameterGroup portParamGroup, ModuleWireGroup packWireGroup, int widthBits, int extraWidth)`
`void` | `ModuleInstance_Standard.MessageStruct_Variable.generatePack(ModuleParameterGroup portParamGroup, ModuleWireGroup packWireGroup, int widthBits, int extraWidth)`
`void` | `ModuleInstance_Standard.MessageUnion_Variable.generatePack(ModuleParameterGroup portParamGroup, ModuleWireGroup packWireGroup, int widthBits, int extraWidth)`
`abstract void` | `ModuleInstance_Standard.Message_Fixed.generateUnpack(Expression source, ModuleWireGroup unpackWireGroup)` Generate the unpacking logic for this message object.
`void` | `ModuleInstance_Standard.MessageSimple.generateUnpack(Expression source, ModuleWireGroup unpackWireGroup)`
`void` | `ModuleInstance_Standard.MessageStruct_Fixed.generateUnpack(Expression source, ModuleWireGroup unpackWireGroup)`
`void` | `ModuleInstance_Standard.MessageUnion_Fixed.generateUnpack(Expression source, ModuleWireGroup unpackWireGroup)`
`void` | `ModuleInstance_Standard.MessageStruct_Variable.generateUnpack(Expression source, ModuleWireGroup unpackWireGroup)`
`void` | `ModuleInstance_Standard.MessageUnion_Variable.generateUnpack(Expression source, ModuleWireGroup unpackWireGroup)`

Method parameters in rdlc.hw with type arguments of type ModuleWireGroup
`protected Module` | `Map.generate(UnitInstance _rootInstance, UnitInstance _unitInstance, java.util.List<ModuleWireGroup> externalWires)` Generate an HDL implementation of the given unit instance in the given root instance.

Constructors in rdlc.hw with parameters of type ModuleWireGroup
`Expression_Operation(int _operation, ModuleWireGroup wireGroup)` Constructor for bit list operations.
`ModuleWireGroup(ModuleWireGroup wireGroup, Instance _instance, boolean forceType, ModuleWire.Type wireType, java.lang.String groupNamePrefix, java.lang.String wireNamePrefix, boolean copyAttributes)` Copy constructor.

Uses of ModuleWireGroup in rdlc.hw.verilog

Fields in rdlc.hw.verilog declared as ModuleWireGroup
`protected ModuleWireGroup` | `XUPEngine.extWires` The external wire group.
`protected ModuleWireGroup` | `S3Engine.extWires` The external wire group.
`protected ModuleWireGroup` | `CaLinx2Engine.extWires` The external wire group.
`protected ModuleWireGroup` | `BEE2Engine.extWires` The external wire group.

Methods in rdlc.hw.verilog that return ModuleWireGroup
`ModuleWireGroup` | `XUPEngine.getExternalWires()`
`ModuleWireGroup` | `S3Engine.getExternalWires()`
`ModuleWireGroup` | `ModelSimEngine.getExternalWires()`
`ModuleWireGroup` | `CaLinx2Engine.getExternalWires()`
`ModuleWireGroup` | `BEE2Engine.getExternalWires()`
`ModuleWireGroup` | `SerialLink.getWires(boolean input)`
`ModuleWireGroup` | `RegisterLink.getWires(boolean input)`

Methods in rdlc.hw.verilog with parameters of type ModuleWireGroup
`protected void` | `OutputFile.printWireGroupDecl(ModuleWireGroup wireGroup)` Print a `ModuleWireGroup` in it's verilog port declaration form.
`protected void` | `OutputFile.printWireGroupList(ModuleWireGroup wireGroup, boolean last)` Print a `ModuleWireGroup` in it's verilog port list form.

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