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## Uses of Package
rdlc.hw

Packages that use rdlc.hw
rdlc.hw | This package contains all the classes to transform an RDL design into a hardware design.
rdlc.hw.verilog | Classes for turning an abstract hardware design into Verilog.

Classes in rdlc.hw used by rdlc.hw
Engine This class is a generator for hardware emulation engines.
Expression This interface represents an HDL expression.
Expression_Constant A constant integer expression.
Expression_Operation Encodes an expression which requires actual computation in hardware.
Expression_Wire An expression which simply references a wire.
ExternalLink Abstract representation of a link which can transport messages off this platform (FPGA).
Library This class represents an abstract hardware library.
LibraryModule This class represents a module, which instead of being constructed dynamically is being loaded verbatim from a library file.
Link Abstract link generator class.
Module Abstracts the details of a hardware module, including input and output wire (port) groups as well as parameter groups.
ModuleInstance_Indirect This class represents an indirect module instance, or in HDL paralance a hierarchical instantiation.
ModuleInstance_Standard This is a standard module instance.
ModuleInstance_Standard.Message_Fixed Abstract class which represents a fixed bitwidth message for the purpose of generating packing and unpacking logic.
ModuleInstance_Standard.Message_Variable Abstract class which represents a variable bitwidth message for the purpose of generating packing and unpacking logic.
ModuleLogic An abstract representation of a simple piece of hardware logic.
ModuleParameter Abstraction of module parameter.
ModuleParameterGroup Abstraction of a group of related hardware parameters or constants.
ModuleWire Abstraction of bus or wire.
ModuleWire.Type Iterator of all the possible wire types.
ModuleWireGroup Abstraction of a group of related wires.

Classes in rdlc.hw used by rdlc.hw.verilog
Engine This class is a generator for hardware emulation engines.
Expression This interface represents an HDL expression.
Expression_Operation Encodes an expression which requires actual computation in hardware.
FileInclude This class abstracts a file which must be simply copied to the output folder from the input folder or some other location.
Library This class represents an abstract hardware library.
LibraryFile This class abstracts a file which must be simply copied to the output folder from the library.
LibraryModule This class represents a module, which instead of being constructed dynamically is being loaded verbatim from a library file.
Link Abstract link generator class.
Link_Standard Standard link generator class from which most links can inherit.
Map This class contains all of the code required to map a complete RDL design to an HDL (verilog) implementation.
Module Abstracts the details of a hardware module, including input and output wire (port) groups as well as parameter groups.
ModuleInstance_Indirect This class represents an indirect module instance, or in HDL paralance a hierarchical instantiation.
ModuleLogic An abstract representation of a simple piece of hardware logic.
ModuleMux An abstract representation of a multiplexorin hardware.
ModuleParameterGroup Abstraction of a group of related hardware parameters or constants.
ModuleWire Abstraction of bus or wire.
ModuleWire.Type Iterator of all the possible wire types.
ModuleWireGroup Abstraction of a group of related wires.
Shell This class encapsulates all of the functionality that one might wish for from an abstract hardware based RAMP shell project.

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