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## rdlc.hw
Class Map

    java.lang.Object
      rdlc.commands.Map.Language
          rdlc.hw.Map

Direct Known Subclasses:
  Map

    public abstract class Map

extends Map.Language

This class contains all of the code required to map a complete RDL design to an HDL (verilog) implementation.

Version:
  $Revision: 1.17 $
Author:
  Greg Gibeling

Field Summary
`protected Library` | `library` The library.
`protected Declaration` | `rootDecl` The root declaration of the project, the module representing the top level units.

Fields inherited from class rdlc.commands.Map.Language
`accurateSim, autoShells, command, config, map`

Constructor Summary
`Map(Map _command, java.lang.String _config, Map _map, java.lang.Boolean _accurateSim, java.lang.Boolean _autoShells)`

Method Summary
`protected Module` | `generate(UnitInstance _rootInstance, UnitInstance _unitInstance, java.util.List<ModuleWireGroup> externalWires)` Generate an HDL implementation of the given unit instance in the given root instance.
`protected void` | `generateChannels(UnitInstance _unitInstance, Unit unit, Namespace namespace, Module module)` Generate the links for all of the channels in a hierarchical unit.

Methods inherited from class rdlc.commands.Map.Language
`backEndPlugin, invoke`

Methods inherited from class java.lang.Object
`clone, equals, finalize, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait`

Field Detail

### rootDecl

    protected Declaration rootDecl

  The root declaration of the project, the module representing the top level units.

### library

    protected Library library

  The library.

Constructor Detail

### Map

    public Map(Map _command,
               java.lang.String _config,
               Map _map,
               java.lang.Boolean _accurateSim,
               java.lang.Boolean _autoShells)

See Also:
  `rdlc.commands.Map.Language#Language(Map, String, rdlc.rdl.Map, Boolean, Boolean)`

Method Detail

### generate

    protected Module generate(UnitInstance _rootInstance,
                              UnitInstance _unitInstance,
                              java.util.List<ModuleWireGroup> externalWires)

  Generate an HDL implementation of the given unit instance in the given root instance. This method is the meat of the RDL to HDL conversion. It will construct both hierarchical and leaf modules for the appropriate units.

  Parameters:
    `_rootInstance` - The root instance of this mapping.
    `_unitInstance` - The unit instance to generate a verilog module.
    `externalWires` - A list of the external wires which must be routed up through this module.
  Returns:
    The module generated for the given `_unitInstance`.

### generateChannels

    protected void generateChannels(UnitInstance _unitInstance,
                                    Unit unit,
                                    Namespace namespace,
                                    Module module)

  Generate the links for all of the channels in a hierarchical unit. This is a separate method for the simple reason that it contains a LOT of code.

  Parameters:
    `_unitInstance` - The unit instance to generate channels for.
    `unit` - The unit which we're dealing with an instance of.
    `namespace` - The namespace the module is being generated in.
    `module` - The verilog module which is being generated.

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