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## rdlc.hw
Interface ExternalLink

All Superinterfaces:
  Link

    public interface ExternalLink

extends Link

Abstract representation of a link which can transport messages off this platform (FPGA). Basically this is a link responsible for connecting to another board or a computer or whatever else.

Version:
  $Revision: 1.7 $
Author:
  Greg Gibeling

Method Summary
`Module` | `getExternalModule()` Get the module responsible for making the eventual external connection.
`ModuleWireGroup` | `getExternalWires()` Simple accessor.
`void` | `setPortLiteral(java.lang.String portLiteral)` Pass the port option from the RDL file into this external link.

Methods inherited from interface rdlc.hw.Link
`generate, getModule, getWires, getWiresName`

Method Detail

### setPortLiteral

    void setPortLiteral(java.lang.String portLiteral)

  Pass the port option from the RDL file into this external link.

  Parameters:
    `portLiteral` - The port literal string from the source RDL.

### getExternalModule

    Module getExternalModule()

  Get the module responsible for making the eventual external connection. This will take the on-chip wires returned through the normal `Link` interface and transfer data to the external wires which should carry it off-chip.

  Returns:
    The external module for this link.

### getExternalWires

    ModuleWireGroup getExternalWires()

  Simple accessor.

  Returns:
    The external wires which must go from the external module to the top level.

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