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## Uses of Class
rdlc.hw.Module

Packages that use Module
rdlc.hw | This package contains all the classes to transform an RDL design into a hardware design.
rdlc.hw.verilog | Classes for turning an abstract hardware design into Verilog.

Uses of Module in rdlc.hw

Subclasses of Module in rdlc.hw
`class` | `LibraryModule` This class represents a module, which instead of being constructed dynamically is being loaded verbatim from a library file.

Fields in rdlc.hw declared as Module
`protected Module` | `Link_Standard.module` The link endpoint module.
`protected Module` | `Library.startDoneModule` The start done module.

Methods in rdlc.hw that return Module
`protected Module` | `Shell.generate(Unit _unit)` Generate the module shell for the given unit.
`protected Module` | `Map.generate(UnitInstance _rootInstance, UnitInstance _unitInstance, java.util.List<ModuleWireGroup> externalWires)` Generate an HDL implementation of the given unit instance in the given root instance.
`Module` | `AggLink.getAggregateModule()` Simple accessor.
`Module` | `ExternalLink.getExternalModule()` Get the module responsible for making the eventual external connection.
`Module` | `Link_Standard.getModule()`
`Module` | `Link.getModule()` Get the local link module, which will then be instantiated in the wrapper.
`Module` | `Library.getStartDoneModule()` Simple accessor.

Methods in rdlc.hw with parameters of type Module
`protected void` | `Map.generateChannels(UnitInstance _unitInstance, Unit unit, Namespace namespace, Module module)` Generate the links for all of the channels in a hierarchical unit.

Constructors in rdlc.hw with parameters of type Module
`ModuleInstance_Standard(Module _module)` Simple constructor, creates a module instance for the given module.

Uses of Module in rdlc.hw.verilog

Methods in rdlc.hw.verilog with parameters of type Module
`protected void` | `OutputFile.printModuleDeclStart(Module module)` Print a module declaration start.

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