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## Package rdlc.hw

This package contains all the classes to transform an RDL design into a hardware design.

See:
Description

Interface Summary
AggLink | Abstraction of an aggregate link: a link which can carry more than one channel.
Engine | This class is a generator for hardware emulation engines.
Expression | This interface represents an HDL expression.
ExternalLink | Abstract representation of a link which can transport messages off this platform (FPGA).
Link | Abstract link generator class.

Class Summary
Expression_Constant | A constant integer expression.
Expression_Operation | Encodes an expression which requires actual computation in hardware.
Expression_Parameter | An expression which simply references a parameter.
Expression_Wire | An expression which simply references a wire.
FileInclude | This class abstracts a file which must be simply copied to the output folder from the input folder or some other location.
Library | This class represents an abstract hardware library.
LibraryFile | This class abstracts a file which must be simply copied to the output folder from the library.
LibraryModule | This class represents a module, which instead of being constructed dynamically is being loaded verbatim from a library file.
Link_Standard | Standard link generator class from which most links can inherit.
Map | This class contains all of the code required to map a complete RDL design to an HDL (verilog) implementation.
Module | Abstracts the details of a hardware module, including input and output wire (port) groups as well as parameter groups.
ModuleInstance_Indirect | This class represents an indirect module instance, or in HDL paralance a hierarchical instantiation.
ModuleInstance_Standard | This is a standard module instance.
ModuleInstance_Standard.Message_Fixed | Abstract class which represents a fixed bitwidth message for the purpose of generating packing and unpacking logic.
ModuleInstance_Standard.Message_Variable | Abstract class which represents a variable bitwidth message for the purpose of generating packing and unpacking logic.
ModuleInstance_Standard.MessageSimple | This class represents a simple fixed width message.
ModuleInstance_Standard.MessageStruct_Fixed | This class represents a fixed width structured message.
ModuleInstance_Standard.MessageStruct_Variable | This class represents a struct where some of the fields down the line are variable size unions.
ModuleInstance_Standard.MessageUnion_Fixed | This class represents a union which has identically sized fields.
ModuleInstance_Standard.MessageUnion_Variable | This class represents a variable width union.
ModuleLogic | An abstract representation of a simple piece of hardware logic.
ModuleMux | An abstract representation of a multiplexorin hardware.
ModuleParameter | Abstraction of module parameter.
ModuleParameterGroup | Abstraction of a group of related hardware parameters or constants.
ModuleWire | Abstraction of bus or wire.
ModuleWireGroup | Abstraction of a group of related wires.
Shell | This class encapsulates all of the functionality that one might wish for from an abstract hardware based RAMP shell project.

Enum Summary
ModuleWire.Type | Iterator of all the possible wire types.

## Package rdlc.hw Description

This package contains all the classes to transform an RDL design into a hardware design. Most of the functionality in this package is derived from it's powerful set of classes and methods for creating abstract hardware designs, which can later be coverted to text in a variety of HDLs.

The project classes contain most of the code specifically meant to transform RDL into hardware, the rest of the code in this package it suitable for general programatical hardware construction.

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